Title :
Fault characterization, testing considerations, and design for testability of BiCMOS logic circuits
Author :
Salama, Aly E. ; Elmasry, Mohamed I.
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
fDate :
6/1/1992 12:00:00 AM
Abstract :
The results of a simulation-based fault characterization study of BiCMOS logic circuits are given. Based on the fault characterization results, the authors have studied different techniques for testing BiCMOS logic circuits. The effectiveness of stuck-at fault testing, stuck-open fault testing, delay fault testing, and current testing in achieving a high level of defect coverage is studied. A novel BiCMOS circuit structure that improves the testability of BiCMOS digital circuits is presented
Keywords :
BIMOS integrated circuits; fault location; integrated circuit testing; integrated logic circuits; logic design; logic testing; BiCMOS logic circuits; current testing; delay fault testing; design for testability; simulation-based fault characterization; stuck-at fault testing; stuck-open fault testing; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Circuit faults; Circuit simulation; Circuit testing; Design for testability; Logic circuits; Logic testing; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
