Title :
A high-efficiency CMOS +22-dBm linear power amplifier
Author :
Ding, Yongwang ; Harjani, Ramesh
Author_Institution :
Silicon Labs. Inc., Austin, TX, USA
Abstract :
Modern wireless communication systems require power amplifiers with high efficiency and high linearity. CMOS is the technology of choice for complete systems on a chip due to its lower costs and high integration levels. However, it has always been difficult to integrate high-efficiency power amplifiers in CMOS. In this paper, we present a new class of operation (parallel A&B) for power amplifiers that improves both their dynamic range and power efficiency. A prototype design of the new amplifier was fabricated in a 0.18-μm CMOS technology. Measurement results show a PAE that is over 44% and the measured output power is +22 dBm. In comparison to a normal class A amplifier, this new design increases the 1-dB compression point (P1dB) by over 3 dB and reduces dc power consumption by over 50% within the linear operating range.
Keywords :
CMOS analogue integrated circuits; power amplifiers; 0.18 micron; 1-dB compression point; CMOS linear power amplifier; class AB amplifier; dc power consumption; high-efficiency power amplifiers; CMOS technology; Costs; Dynamic range; High power amplifiers; Linearity; Operational amplifiers; Power amplifiers; Power measurement; Prototypes; Wireless communication; CMOS; Class A; class AB; power amplifier;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2005.848179
