Title :
A single-chip dual-band direct-conversion IEEE 802.11a/b/g WLAN transceiver in 0.18-μm CMOS
Author :
Zhang, Pengfei ; Der, Lawrence ; Guo, Dawei ; Sever, Isaac ; Bourdi, Taoufik ; Lam, Christopher ; Zolfaghari, Alireza ; Chen, Jess ; Gambetta, Douglas ; Cheng, Baohong ; Gowder, Sujatha ; Hart, Siegfried ; Huynh, Lam ; Nguyen, Thai ; Razavi, Behzad
Author_Institution :
RF Micro Devices, San Jose, CA, USA
Abstract :
This paper presents a single-chip dual-band CMOS direct-conversion transceiver fully compliant with the IEEE 802.11a/b/g standards. Operating in the frequency ranges of 2.412-2.484 GHz and 4.92-5.805 GHz (including the Japanese band), the fractional-N PLL based frequency synthesizer achieves an integrated (10 kHz-10 MHz) phase noise of 0.54°/1.1° for 2/5-GHz band. The transmitter error vector magnitude (EVM) is -36/-33 dB with an output power level higher than -3/-5dBm and the receiver sensitivity is -75/-74 dBm for 2/5-GHz band for 64QAM at 54 Mb/s.
Keywords :
CMOS integrated circuits; IEEE standards; UHF integrated circuits; frequency synthesizers; microwave integrated circuits; phase locked loops; transceivers; wireless LAN; 0.18 micron; 2.412 to 2.484 GHz; 4.92 to 5.805 GHz; 54 Mbit/s; 64QAM; CMOS direct-conversion transceiver; IEEE 802.1 la/b/g WLAN transceiver; error vector magnitude; fractional phase locked loop; frequency synthesizer; orthogonal frequency division multiplexing; phase noise; wireless local area network; Baseband; Costs; Dual band; Frequency synthesizers; OFDM; Phase locked loops; Radio transmitters; Transceivers; Voltage-controlled oscillators; Wireless LAN; CMOS transceiver; IEEE 802.11; direct conversion; fractional phase locked loop; orthogonal frequency division multiplexing (OFDM); wireless local area network (WLAN);
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2005.848182
