Three-dimensional model of gate current flow in thyristor. I. Description

The digital gate concept is one of the fundamental ways leading to improvement of the dynamic rates of a thyristor. The distribution of the current density of the gate-cathode junction along the edge of the gate contact must, however, be as uniform as possible. A numerical model which permits determination of this distribution, the initial turn-on area, and their dependence on constructional parameters is proposed. The three-dimensional model includes the gate contact layer, the cathode layer, and the p-base layer. It consists of two coupled submodels: a one-dimensional submodel describing the current flow through the arm of the gate contact, and a two-dimensional one modeling the current flow inside the semiconductor bulk of the thyristor. The second submodel was developed in two versions: an exact 2-D submodel based on the solution of the semiconductor structure equations, and a lumped-parameter GP submodel based on the Gummel-Poon approach. The proposed model allows fast multiple analysis even on a personal computer