A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories

Author

Siu, Joseph Wai Kit ; Eslami, Yadollah ; Sheikholeslami, Ali ; Gulak, P. Glenn ; Endo, Toru ; Kawashima, Shoichiro

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Toronto, Ont., Canada

Volume

38

Issue

3

fYear

2003

fDate

3/1/2003 12:00:00 AM

Firstpage

541

Lastpage

549

Abstract

A reference generation scheme is proposed for a 1T-1C ferroelectric random-access memory (FeRAM) architecture that balances fatigue evenly between memory cells and reference cells. This is achieved by including a reference cell per row (instead of per column) of the memory array. The proposed scheme converts the bitline voltage to current and compares this current against a reference current using a current-steering sense amplifier. This scheme is evaluated over a range of bitline lengths and cell sizes in a 16-Kb test chip implemented in a 0.35-μm FeRAM process. The test chip measures an access time of 62 ns at room temperature using a 3-V power supply.

Keywords

cellular arrays; ferroelectric storage; random-access storage; reference circuits; 0.35 micron; 16 Kbit; 1T-1C ferroelectric random-access memories; 3 V; 62 ns; FeRAM; access time; bitline lengths; bitline voltage; cell sizes; current-based reference-generation scheme; current-steering sense amplifier; reference current; Fatigue; Ferroelectric films; Ferroelectric materials; Memory architecture; Nonvolatile memory; Power measurement; Random access memory; Semiconductor device measurement; Testing; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.808289

Filename

1183870