Impurity diffusion behavior of bipolar transistor under low-temperature furnace annealing and high-temperature RTA and its optimization for 0.5-μm Bi-CMOS process

Author

Norishima, Masayuki ; Iwai, Hiroshi ; Niitsu, Youichiro ; Maeguchi, Kenji

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

39

Issue

1

fYear

1992

fDate

1/1/1992 12:00:00 AM

Firstpage

33

Lastpage

40

Abstract

A low-temperature-processed (800-850°C) bipolar transistor design suitable for the high-performance 0.5-μm BiCMOS process is discussed. It has been found that insufficient activation of arsenic in the emitter, enhanced boron diffusion in the low-concentration base region. and insufficient arsenic diffusion from the poly Si are serious considerations if low-temperature furnace annealing is used. If high-temperature rapid thermal annealing (RTA) is used instead of low-temperature furnace annealing, these problems are resolved. Through impurity diffusion behavior and related electrical bipolar transistor design in the high-performance 0. 5-μm Bi-CMOS process are proposed. The As-P emitter and selectively implanted collector structures, annealed using RTA, were found to be suitable for the advanced Bi-CMOS process

Keywords

BIMOS integrated circuits; bipolar transistors; diffusion in solids; incoherent light annealing; integrated circuit technology; ion implantation; 0.5 micron; As-P emitter structure; Bi-CMOS process; Si; Si:As,P; Si:B; bipolar transistor; electrical bipolar transistor design; high-temperature RTA; impurity diffusion; ion implantation; low-temperature furnace annealing; selectively implanted collector structures; Bipolar transistors; Boron; CMOS process; Epitaxial layers; Fabrication; Furnaces; Impurities; Production; Rapid thermal annealing; Temperature;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.108209

Filename

108209