Comparison of Dual-Rail and TMR Logic Cost Effectiveness and Suitability for FPGAs With Reconfigurable SEU Tolerance

Author

Shuler, Robert L. ; Bhuva, Bharat L. ; O´Neill, Patrick M. ; Gambles, Jody W. ; Rezgui, Sana

Author_Institution

Johnson Space Center, Houston, TX

Volume

56

Issue

1

fYear

2009

Firstpage

214

Lastpage

219

Abstract

We compare four circuit methods for single event (SE) mitigation: single string with radiation-hardened flip flops, delay-guarded logic, dual-rail logic, and triple modular redundancy (TMR). Test results of the circuit methods at 180 nm are presented. We then describe a novel reprogrammable FPGA architecture which can be configured based on SE mitigation and performance needs, and we evaluate the candidate SE mitigation methods as to suitability for such architecture.

Keywords

delays; field programmable gate arrays; flip-flops; radiation hardening (electronics); redundancy; delay-guarded logic circuits; dual-rail logic circuits; radiation-hardened flip flops; reconfigurable SEU tolerance; reprogrammable FPGA architecture; single event mitigation; triple modular redundancy logic circuits; Circuit testing; Costs; Field programmable gate arrays; Hardware; Logic circuits; Manufacturing; Protection; Reconfigurable logic; Redundancy; Single event upset; Complementary metal-oxide-semiconductor (CMOS); digital circuits; field programmable gate array (FPGA); radiation-hardening; sequential circuits; single event;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2008.2010320

Filename

4782164