The design of concurrent error diagnosable systolic arrays for band matrix multiplications

The characteristics of a systolic array and the important issues in fault-tolerant systolic computing are presented. Recent efforts to optimize the performance of a band matrix multiplication systolic array (BMMSA) is discussed, concentrating on the fundamental differences between the Kung-Leiserson and Huang-Abraham schemes of systolic design in order to exemplify the extremes in design philosophies. The motivations for additional figures of merit are pointed out, and a novel BMMSA design is introduced. An efficient scheme, based on the time-redundancy technique of RESO (recomputation with shifted operands), is applied to the design of CED-capable BMMSAs. Different designs, based on the Kung-Leiserson BMMSA, the proposed BMMSA, and the Huang-Abraham BMMSA, are presented