SEU reliability improvement due to source-side charge collection in the deep-submicron SRAM cell

Author

Saxena, Prashant Kumar ; Bhat, Navakanta

Author_Institution

Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India

Volume

3

Issue

1

fYear

2003

fDate

3/1/2003 12:00:00 AM

Firstpage

14

Lastpage

17

Abstract

The effect of technology scaling (0.5-0.09 μm) on single event upset (SEU) phenomena is investigated using full two-dimensional device simulation. The SEU reliability parameters, such as critical charge (Q_crit), feedback time (T_fd) and linear energy transfer (LET), are estimated. For L_g<0.18 μm, the source node collects a significant fraction of radiation-induced charge resulting in an increase of LET, despite the lower critical charge at the sensitive drain node. The effect of striking location on LET confirms this finding.

Keywords

SRAM chips; ULSI; circuit simulation; integrated circuit reliability; radiation effects; 0.5 to 0.09 micron; SEU reliability; critical charge; deep-submicron SRAM cell; drain node; feedback time; linear energy transfer; radiation-induced charge; single event upset; source node; source-side charge collection; technology scaling; two-dimensional device simulation; CMOS technology; Discrete event simulation; Energy exchange; Feedback; Leakage current; MOS devices; MOSFETs; Random access memory; Reliability engineering; Single event upset;

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2003.808979

Filename

1184104