Title :
SEU reliability improvement due to source-side charge collection in the deep-submicron SRAM cell
Author :
Saxena, Prashant Kumar ; Bhat, Navakanta
Author_Institution :
Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
fDate :
3/1/2003 12:00:00 AM
Abstract :
The effect of technology scaling (0.5-0.09 μm) on single event upset (SEU) phenomena is investigated using full two-dimensional device simulation. The SEU reliability parameters, such as critical charge (Qcrit), feedback time (Tfd) and linear energy transfer (LET), are estimated. For Lg<0.18 μm, the source node collects a significant fraction of radiation-induced charge resulting in an increase of LET, despite the lower critical charge at the sensitive drain node. The effect of striking location on LET confirms this finding.
Keywords :
SRAM chips; ULSI; circuit simulation; integrated circuit reliability; radiation effects; 0.5 to 0.09 micron; SEU reliability; critical charge; deep-submicron SRAM cell; drain node; feedback time; linear energy transfer; radiation-induced charge; single event upset; source node; source-side charge collection; technology scaling; two-dimensional device simulation; CMOS technology; Discrete event simulation; Energy exchange; Feedback; Leakage current; MOS devices; MOSFETs; Random access memory; Reliability engineering; Single event upset;
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
DOI :
10.1109/TDMR.2003.808979
