Optimization of single-gate carbon-nanotube field-effect transistors

The performance of Schottky-barrier carbon-nanotube field-effect transistors (CNTFETs) critically depends on the device geometry. Asymmetric gate contacts, the drain and source contact thickness, and inhomogenous dielectrics above and below the nanotube influence the device operation. An optimizer has been used to extract geometries with steep subthreshold slope and high I_on/I_off ratio. It is found that the best performance improvements can be achieved using asymmetric gates centered above the source contact, where the optimum position and length of the gate contact varies with the oxide thickness. The main advantages of geometries with asymmetric gate contacts are the increased I_on/I_off ratio and the fact that the gate voltage required to attain minimum drain current is shifted toward zero, whereas symmetric geometries require V_g=V_d/2. Our results suggest that the subthreshold slope of single-gate CNTFETs scales linearly with the gate-oxide thickness and can be reduced by a factor of two reaching a value below 100 mV/dec for devices with oxide thicknesses smaller than 5 nm by geometry optimization.