Title :
TRIM: testability range by ignoring the memory
Author :
Carter, L. ; Huisman, L.M. ; Williams, T.W.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
1/1/1988 12:00:00 AM
Abstract :
The testability by random test patterns of faults in the logic surrounding embedded RAMs is studied. Upper and lower bounds on the probability that a fault is caught are obtained by analyzing a modified, purely combinational circuit without the RAM. This analysis can be done with standard testability analysis techniques. The analysis is applied to an embedded two-port RAM
Keywords :
integrated circuit testing; integrated memory circuits; logic testing; random-access storage; TRIM; combinational circuit; embedded RAMs; embedded two-port RAM; faults; logic; lower bounds; probability; random test patterns; testability analysis; upper bounds; Automatic testing; Circuit faults; Circuit testing; Combinational circuits; Logic devices; Logic testing; Random access memory; Read-write memory; Upper bound; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
