DocumentCode :
1158329
Title :
Placement Algorithm in Analog-Layout Designs
Author :
Zhang, Lihong ; Raut, Rabin ; Jiang, Yingtao ; Kleine, Ulrich
Author_Institution :
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que.
Volume :
25
Issue :
10
fYear :
2006
Firstpage :
1889
Lastpage :
1903
Abstract :
Analog macrocell placement is an NP-hard problem. This paper presents an attempt to solve this problem by using the optimization flow of a genetic algorithm (GA) enhanced by simulated annealing (SA). The bit-matrix representation is employed to improve the search efficiency. In particular, to reduce the solution space without degrading search opportunities, the technique of cell slide is deployed to transform an absolute placement to a relative placement. Following this cell-slide process, it is proved that, for an initial placement, there always exists a solution that can guarantee no occurrence of overlaps among cells and meet any applicable symmetry constraints pertaining to analog layouts. For the optimization of the algorithm parameters, the fractional factorial experiment using an orthogonal array has been conducted, and the exact parameter values are determined using a meta-GA approach. The experimental results show that, compared with the SA approach, the proposed algorithm consumes less computation time while generating higher quality layouts, comparable to expert manual placements
Keywords :
analogue integrated circuits; circuit optimisation; genetic algorithms; integrated circuit layout; simulated annealing; analog-layout designs; bit-matrix representation; cell-slide process; fractional factorial experiment; genetic algorithm; meta-GA approach; orthogonal array; placement algorithm; simulated annealing; Algorithm design and analysis; Analog circuits; Degradation; Design automation; Genetic algorithms; Integrated circuit layout; Integrated circuit synthesis; Macrocell networks; NP-hard problem; Simulated annealing; Analog integrated circuits (ICs); genetic algorithm (GA); layout of integrated circuits; simulated annealing (SA);
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2005.860957
Filename :
1677679
Link To Document :
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