Title :
Modeling and Analysis of Leakage Currents in Double-Gate Technologies
Author :
Mukhopadhyay, Saibal ; Kim, Keunwoo ; Chuang, Ching Te ; Roy, Kaushik
Author_Institution :
Dept. of Electr. Eng., Purdue Univ., West Lafayette, IN
Abstract :
This paper models and analyzes subthreshold and gate leakage currents in different double-gate (DG) devices, namely, a doped body symmetric device with polysilicon gates, an intrinsic body symmetric device with metal gates, and an intrinsic body asymmetric device with different front and back gate materials. The effect of variations in device parameters on the leakage components is also analyzed. Using the developed models, digital circuits (logic gates and static random access memory cells) designed with different DG structures are also analyzed. The analysis shows that the use of (near mid-gap) metal gate and intrinsic body devices significantly reduces both the total leakage and its sensitivity to parametric variations in DG devices and circuits
Keywords :
SRAM chips; leakage currents; logic gates; back gate materials; digital circuits; doped body symmetric device; double-gate devices; double-gate technologies; front gate materials; gate leakage currents; intrinsic body asymmetric device; intrinsic body symmetric device; logic gates; metal gates; polysilicon gates; static random access memory cells; subthreshold leakage currents; Circuit synthesis; Digital circuits; Doping; Gate leakage; Inorganic materials; Leakage current; MOS devices; Paper technology; Subthreshold current; Tunneling; Double-gate transistor; gate leakage; modeling; subthreshold leakage;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2006.873892
