DocumentCode :
1158529
Title :
Simulating Resistive-Bridging and Stuck-At Faults
Author :
Engelke, Piet ; Polian, Ilia ; Renovell, Michel ; Becker, Bernd
Author_Institution :
Albert-Ludwigs-Univ., Freiburg
Volume :
25
Issue :
10
fYear :
2006
Firstpage :
2181
Lastpage :
2192
Abstract :
The authors present a simulator for resistive-bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look up, thus, exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; interaction of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances. Experimental results are given for resistive-bridging and stuck-at faults in combinational and sequential circuits. Different definitions of fault coverage are listed, and quantitative results with respect to all these definitions are given for the first time
Keywords :
fault simulation; logic testing; sequential circuits; bridge resistance; fault simulation; probabilistic fault coverage; resistive stuck-at faults; resistive-bridging faults; sequential circuits; Automatic test pattern generation; Bridge circuits; Circuit faults; Circuit simulation; Circuit testing; Equations; Microelectronics; Redundancy; Sequential circuits; Shape; Bridging fault simulation; probabilistic fault coverage; resistive stuck-at faults; resistive-bridging faults;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2006.871626
Filename :
1677700
Link To Document :
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