DocumentCode :
1158582
Title :
Testability of SPP Three-Level Logic Networks in Static Fault Models
Author :
Ciriani, Valentina ; Bernasconi, Anna ; Drechsler, Rolf
Volume :
25
Issue :
10
fYear :
2006
Firstpage :
2241
Lastpage :
2248
Abstract :
Full testability is a desirable property for a minimal logic network. The classical minimal two-level sum of products (SOP) networks are fully testable in some standard fault models. In this paper, the authors investigate the testability of recently introduced three-level logic forms sum of pseudoproducts (SPP), which allow the representation of Boolean functions with much shorter expressions than two-level forms. The authors study their testability under static fault models (FMs), i.e., the stuck-at-fault model (SAFM) and the cellular fault model (CFM). For SPP networks, several minimal forms can be considered. While full testability can be proven in the SAFM for some forms, SPP networks in the CFM are shown to contain redundancies. Finally, the authors propose a method for transforming nontestable networks into testable ones. In the SAFM, the resulting irredundant networks are still minimal. The experimental results are given to demonstrate the efficiency of the approach
Keywords :
design for testability; logic testing; ternary logic; Boolean functions; SPP three-level logic networks; cellular fault model; design for testability; logic synthesis; minimal logic network; static fault models; stuck-at-fault model; sum of pseudoproducts; two-level sum of products networks; Boolean functions; Circuit faults; Circuit synthesis; Circuit testing; Computer science; Flexible manufacturing systems; Intelligent networks; Logic testing; Minimization; Network synthesis; Design for testability; logic synthesis; test synthesis; testing;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2005.862746
Filename :
1677706
Link To Document :
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