Design of large embedded CMOS PLAs for built-in self-test

A novel scheme to design built-in self-test programmable logic arrays (PLAs) implemented with CMOS technology is described, which is attractive for large arrays. These PLAs can perform function-independent self-test at normal operating speed, can detect CMOS switch-level faults, and have a lower area overhead than any other BIST scheme. A sequential parity checking technique is used to test for the AND and OR arrays of the PLA. This technique does not require any XOR cascade to evaluate parity data as in the parallel checking technique used by other schemes, thus achieving an order of magnitude reduction in total testing time. The method accounts for switch-level stuck-open and stuck-on faults in addition to conventional stuck-at, crosspoint, and bridging faults. A novel circuit design technique was used to implement the test pattern generator for product lines. It makes use of a Johnson counter and a two-level decoding network to obtain a very low area overhead and to match the pitch between the PLA and the test circuitry