A signal processor for median-based algorithms

Author

Vainio, Olli ; Neuvo, Yrjö ; Butner, steven E.

Author_Institution

Comput. Syst. Lab., Tampere Univ. of Technol., Finland

Volume

37

Issue

9

fYear

1989

fDate

9/1/1989 12:00:00 AM

Firstpage

1406

Lastpage

1414

Abstract

A sorter-based processor architecture is introduced for digital signal processing purposes. The processor has been optimized to implement sliding average-type linear structures and three- and five-sample sorting operations. The specialized processor can be used, for example, for the several variations of the finite-impulse-response (FIR) median hybrid (FMH) filters, as well as other types of ranked-order filters and running-sum averaging operations. FMH filters with averaging substructures and window lengths of up to 65 samples can be computed with sampling intervals of less than 20 clock cycles. The 12-bit microprogrammable core processor is designed as a full-custom very large scale integration (VLSI) circuit. Examples of filter implementations show that the sorter-based processor architecture is suitable for several kinds of digital signal processing tasks

Keywords

VLSI; computerised signal processing; digital signal processing chips; 12-bit microprogrammable core processor; DSP chips; FIR; FMH; VLSI; digital signal processing; finite-impulse-response; median hybrid; median-based algorithms; signal processor; sorter-based processor; Circuits; Clocks; Digital signal processing; Finite impulse response filter; Process design; Signal processing; Signal processing algorithms; Signal sampling; Sorting; Very large scale integration;

fLanguage

English

Journal_Title

Acoustics, Speech and Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

0096-3518

Type

jour

DOI

10.1109/29.31294

Filename

31294