Title :
A new approach to the design of built-in self-testing PLAs for high fault coverage
Author :
Upadhyaya, Shambhu J. ; Saluja, Kewal K.
Author_Institution :
Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
fDate :
1/1/1988 12:00:00 AM
Abstract :
Four critical requirements are identified for the built-in self-testing of programmable logic arrays (BIST PLAs): the test set to test the PLA as well as the output response must be independent of the function of the PLA; the test pattern generator (TPG) and the response evaluator circuits must be simple to keep the extra logic overhead to a minimum; the fault coverage of the PLA must be within acceptable limits; and the speed of the test application must be high. A design that meets all of these goals is proposed. The approach is based on counting crosspoints, as opposed to the conventional parity technique. The TPG and RE circuits are simple and consist of shift registers and counters. The design requires a reorganization of the columns of the PLA on the basis of the number of crosspoints. This design provides extremely high fault coverage: the coverage for multiple faults is higher than that of any BIST design known to the authors, and the single-fault coverage is 100%. The design is simple and can easily be incorporated into existing computer-aided design systems
Keywords :
automatic testing; cellular arrays; integrated logic circuits; logic CAD; logic testing; BIST PLAs; RE circuits; TPG; built-in self-testing PLAs; computer-aided design systems; counters; crosspoints; fault coverage; output response; response evaluator circuits; shift registers; speed; test pattern generator; test set; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Fault diagnosis; Logic circuits; Logic testing; Programmable logic arrays; Shift registers; Test pattern generators;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
