Title :
Analysis of the Spur Characteristics of Edge-Combining DLL-Based Frequency Multipliers
Author :
Casha, Owen ; Grech, Ivan ; Badets, Franck ; Morche, Dominique ; Micallef, Joseph
Author_Institution :
Dept. of Microelectron. & Nanoelectron., Univ. of Malta, Msida
Abstract :
A complete analysis of the spur characteristics of edge-combining delay-locked loop (DLL)-based frequency multipliers is presented in this brief. The novelty of this analysis is the fact that it can be used to estimate the effect of both the in-lock error and the delay-stage mismatch on the spurious level of the frequency multiplier with low computational complexity. In addition, a way to reduce the mismatch between the delay cells in the delay line is discussed via an analytic model and verified by the implementation of a delay cell in a 65-nm CMOS process.
Keywords :
CMOS integrated circuits; computational complexity; delay lock loops; frequency multipliers; CMOS process; computational complexity; delay-locked loop; delay-stage mismatch; edge-combining DLL-based frequency multipliers; in-lock error; spur characteristics; Delay mismatch; delay-locked loop (DLL); frequency synthesis; in-lock error; spurious level;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2008.2011605
