Improvement of short-channel characteristics of a 0.1-μm PMOSFET with ultralow-temperature nitride spacer by using a novel oxide capped boron uphill treatment

Author

Yang, C.W. ; Fang, Y.K. ; Chen, C.H. ; Wang, W.D. ; Ting, S.F. ; Chen, S.F. ; Cheng, J.Y. ; Wang, M.F. ; Chen, C.L. ; Yao, L.G. ; Lee, T.L. ; Chen, S.C. ; Yu, C.H. ; Liang, M.S.

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

Volume

24

Issue

1

fYear

2003

Firstpage

43

Lastpage

45

Abstract

The thermal annealing at 720/spl deg/C for 2 hr (called boron uphill treatment) with an SiO₂-capped layer was applied after source/drain extensions (SDE) implantation to improve the short channel characteristics of a 0.1-μm PMOSFET with an ultra-low temperature nitride spacer. The influence and the mechanism of the capped layer on this uphill treatment were investigated. The results show that the capped layer treatment indeed leads to a shallower junction, improved V/sub th/ roll-off characteristic, and added immunity against subsurface punchthrough.

Keywords

MOSFET; annealing; boron; capacitance; ion implantation; 0.1 micron; 2 h; 720 degC; PMOSFET; SiO/sub 2/-Si:B; SiO/sub 2/-capped layer; oxide capped B uphill treatment; p-channel MOSFET; short channel characteristics; source/drain extensions implantation; subsurface punchthrough immunity; thermal annealing; threshold voltage roll-off characteristic; ultra-low temperature nitride spacer; Annealing; Boron; CMOS technology; Ion implantation; Laboratories; MOSFET circuits; Plasma temperature; Silicon; Very large scale integration;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2002.807312

Filename

1185205