A Compact Physical Model for Yield Under Gate Length and Body Thickness Variations in Nanoscale Double-Gate CMOS

Double-gate (DG) CMOS is projected to replace classical bulk and silicon-on-insulator technologies around the 32-nm node. Predicting the impact of process variations on yield for these devices is necessary at an early stage of the design cycle to enable optimal technology and circuit design choices. This paper presents a compact physical model for DG leakage and threshold voltage distribution due to gate length L and body thickness t_si variations, both for single devices and multiple-device stacks. The model is derived directly from the solution of Poisson and Schrodinger equations and thus captures the effect of unique DG phenomena such as volume inversion and quantum confinement. The model is verified for devices at the end of the scaling roadmap (L=13nm, t_si=3nm), with the yield estimation error less than 3% compared to the Monte Carlo simulation for a 3sigma variation of as much as 20% of the nominal process parameters