Title :
On single row routing
Author :
Saxena, Sanjeev ; Prasad, V.C.
Author_Institution :
Indian Inst. of Technol., New Delhi, India
fDate :
7/1/1989 12:00:00 AM
Abstract :
A parallel algorithm for the single-row routing problem without backward moves and interstreet crossings is presented. The algorithm requires O(log N log log N) time with N processors on a concurrent-read-concurrent-write shared-memory model or alternatively O(log2 N) time with N processors on a concurrent-read-exclusive-write shared-memory model. The algorithm is then modified to run sequentially in O(N) time
Keywords :
circuit layout CAD; parallel algorithms; concurrent-read-concurrent-write shared-memory model; concurrent-read-exclusive-write shared-memory model; parallel algorithm; single row routing; Circuits and systems; Computer science; Conductors; Read-write memory; Routing;
Journal_Title :
Circuits and Systems, IEEE Transactions on
