DocumentCode
1161710
Title
A floating-point VLSI chip for the TRON architecture: an architecture for reliable numerical programming
Author
Kawasaki, Shumpei ; Watabe, Mitsuru ; Morinaga, Shigeki
Author_Institution
Hitachi Ltd., Tokyo, Japan
Volume
9
Issue
3
fYear
1989
fDate
6/1/1989 12:00:00 AM
Firstpage
26
Lastpage
44
Abstract
A description is given of the Gmicro/FPU (floating-point unit), a chip that provides floating-point instructions for both the Gmicro/200 and the Gmicro/300 microprocessors. The VLSI central-processing-unit architecture, for which it is designed, defines 23 coprocessor instructions, some of which are designed to be used in the floating-point instructions. Some background information is given, and the requirements, architecture, implementation, and evaluation of the Gmicro/FPU are discussed.<>
Keywords
VLSI; computer architecture; microprocessor chips; Gmicro/200; Gmicro/300; Gmicro/FPU; TRON architecture; coprocessor instructions; floating-point VLSI chip; implementation; microprocessors; reliable numerical programming; requirements; Central Processing Unit; Computer architecture; Coprocessors; Floating-point arithmetic; Intelligent networks; Intelligent robots; Libraries; Manufacturing; Microprocessors; Very large scale integration;
fLanguage
English
Journal_Title
Micro, IEEE
Publisher
ieee
ISSN
0272-1732
Type
jour
DOI
10.1109/40.31476
Filename
31476
Link To Document