A video codec LSI for high-definition TV systems with one-transistor DRAM line memories

Author

Takada, Tomoji ; Oto, Takeshi ; Kitagaki, Kazukuni ; Hatanaka, Naoyuki ; Demura, Tatsuhiko ; Fuji, Hiromichi ; Odaka, Toshinori ; Sue, Hiroshi ; Oku, Tadahiro

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

24

Issue

6

fYear

1989

fDate

12/1/1989 12:00:00 AM

Firstpage

1656

Lastpage

1661

Abstract

A video codec LSI for high-definition television (HDTV) systems has been developed. By using a time-compressed integration encoding technique, it converts a 20.0-MHz bandwidth luminance signal and two 5.0-MHz chrominance signals into a compressed image signal at 48.6-MHz sampling frequency. It is useful in many HDTV application systems, such as 400-Mb/s digital transmission system, a video disk player system, or an analog transmission system. Over 288000 elements, including a 52-kb one-transistor DRAM (dynamic random access memory) line memory specially developed for this LSI, were integrated on a 12.16×12.10-mm² chip. A standard cell layout method and a 1.2-μm CMOS logic LSI process were used

Keywords

CMOS integrated circuits; codecs; digital communication systems; high definition television; large scale integration; random-access storage; television equipment; video equipment; 1.2 micron; 20 MHz; 400 Mbit/s; 48.6 MHz; 5 MHz; 52 kbit; CMOS logic LSI process; HDTV; analog transmission system; chrominance signals; compressed image signal; digital transmission system; dynamic random access memory; high-definition TV systems; luminance signal; one-transistor DRAM line memories; sampling frequency; standard cell layout; time-compressed integration encoding; video codec LSI; video disk player system; Bandwidth; Frequency conversion; HDTV; Image coding; Image converters; Image sampling; Large scale integration; TV; Video codecs; Video compression;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.45002

Filename

45002