DocumentCode
1161968
Title
High voltage SOI SJ-LDMOS with dynamic back-gate voltage
Author
Wang, W.L. ; Zhang, Boming ; Chen, W.J. ; Li, Z.J.
Author_Institution
State Key Lab. of Electron. Thin Films & Integrated Devices, Univ. of Electron. Sci. & Technol. of China, Chengdu
Volume
45
Issue
4
fYear
2009
Firstpage
233
Lastpage
235
Abstract
The impact of dynamic back-gate voltage on SOI SJ-LDMOS (super junction LDMOS on silicon-on-insulator) is investigated. The variable back-gate voltage induces the holes besides electrons below the buried oxide layer, which optimises the substrate-assisted depletion effect and promotes the charge balance between N and P pillars of SJ. As a result, the uniform electric field is achieved, resulting in improving breakdown voltage. In addition, SJ-LDMOS with dynamic back-gate voltage keeps the low on-resistance, in contrast to the conventional LDMOS with positive back-gate voltage which increases on-resistance because of weakening RESURF effect.
Keywords
MOS integrated circuits; silicon-on-insulator; dynamic back-gate voltage; high voltage SOI SJ-LDMOS; silicon-on-insulator; substrate-assisted depletion effect; super junction LDMOS; variable back-gate voltage;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20093005
Filename
4784327
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