• DocumentCode
    1162932
  • Title

    A new approach to topological via minimization

  • Author

    Sarrafzadeh, Majid ; Lee, D.T.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
  • Volume
    8
  • Issue
    8
  • fYear
    1989
  • fDate
    8/1/1989 12:00:00 AM
  • Firstpage
    890
  • Lastpage
    900
  • Abstract
    A topological via minimization problem in a two-layer routing environment is examined. The problem of minimizing the number of vias needed to route n two-terminal nets in a bounded routing region is shown to be NP-hard. However, in the case of a two-shore routing region, the topological via minimization problem can be solved in O(n2 log n) time. As a basis for the algorithm, a two-chain maximum dominance problem, which is of interest in its own right, is considered, and its applications to other very large-scale integration layout problems are shown
  • Keywords
    VLSI; circuit layout; computational complexity; minimisation; network topology; NP-hard; VLSI; bounded routing; circuit layout; minimization; network topology; two-chain maximum dominance problem; two-layer routing environment; two-shore routing; two-terminal nets; Integrated circuit interconnections; Joining processes; Microelectronics; Minimization; Polynomials; Routing; Topology; Wires;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.31548
  • Filename
    31548