DocumentCode
1162988
Title
Small-signal analysis and minimum settling time design of a one-stage folded-cascode CMOS operational amplifier
Author
Yang, Howard C. ; Abu-Dayeh, Mahmoud A. ; Allstot, David J.
Author_Institution
Chips & Technol., Inc., San Jose, CA, USA
Volume
38
Issue
7
fYear
1991
fDate
7/1/1991 12:00:00 AM
Firstpage
804
Lastpage
807
Abstract
A small-signal analysis of the single-ended one-stage folded-cascode CMOS operational amplifier is presented. The analysis results in a four-pole two-zero representation from which a two-pole model is extracted that is sufficiently accurate for many applications in switched-capacitor (SC) circuits. A design equation for obtaining the minimum settling time (MST) response for SC applications is given
Keywords
CMOS integrated circuits; linear integrated circuits; operational amplifiers; SC applications; four-pole two-zero representation; minimum settling time design; one-stage folded-cascode CMOS operational amplifier; small-signal analysis; switched capacitor circuits; two-pole model; Circuits; Entropy; Equations; Frequency; Operational amplifiers; Semiconductor device modeling; Sensor arrays; Signal processing algorithms; Spectral analysis; Speech processing;
fLanguage
English
Journal_Title
Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0098-4094
Type
jour
DOI
10.1109/31.135753
Filename
135753
Link To Document