Title :
Compilation for FPGA-based reconfigurable hardware
Author :
Cardoso, João M P ; Neto, Horácio C.
Author_Institution :
Fac. of Sci. & Technol., Univ. of Algarve, Faro, Portugal
Abstract :
This paper provides techniques for compiling software programs into reconfigurable hardware which offer faster and more efficient performance than the complex resource-sharing approaches typical of high-level synthesis systems. The Java-based compiler presented in this paper uses intermediate graph representations to embody parallelism at various levels.
Keywords :
Java; field programmable gate arrays; high level synthesis; program compilers; reconfigurable architectures; FPGA-based reconfigurable hardware compilation; Java-based compiler; high-level synthesis systems; intermediate graph representations; resource-sharing approaches; software programs compilation; Computer architecture; Field programmable gate arrays; Hardware design languages; High level languages; High level synthesis; Java; Parallel processing; Partitioning algorithms; Program processors; Software performance;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2003.1188264
