A CMOS analog continuous-time delay line with adaptive delay-time control

Author

Bult, Klaas ; Wallinga, Hans

Author_Institution

Dept. of Electr. Eng., Twente Univ., Enschede, Netherlands

Volume

23

Issue

3

fYear

1988

fDate

6/1/1988 12:00:00 AM

Firstpage

759

Lastpage

766

Abstract

A CMOS analog continuous-time delay line composed of cascaded first-order current-domain all-pass sections is discussed. Each all-pass section consists of CMOS transistors and a single capacitor. The operation is based on the square-law characteristic of an MOS transistor in saturation. The delay time per section can either be controlled by an external voltage or locked to an external reference frequency by means of a control system which features a large capture range. Experimental verification has been performed on two setups: an integrated cascade of 26 identical all-pass sections and a frequency-locking system breadboard built around two identical on-chip all-pass sections.<>

Keywords

CMOS integrated circuits; active networks; all-pass filters; delay lines; CMOS; CMOS transistors; MOS transistor in saturation; adaptive delay-time control; analog continuous-time delay line; cascaded first-order current-domain all-pass sections; external reference frequency; external voltage; frequency-locking system breadboard; integrated cascade; large capture range; operation; single capacitor; square-law characteristic; Adaptive control; Circuits; Control systems; Delay lines; Filters; Frequency; Inverters; MOSFETs; Programmable control; Transfer functions;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.316

Filename

316