Title :
Methodology for submicron device model development
Author :
Marash, Vered ; Dutton, Robert W.
Author_Institution :
Integrated Circuit Lab., Stanford Univ., CA, USA
fDate :
2/1/1988 12:00:00 AM
Abstract :
Two-dimensional (2-D) device analysis is coupled into a new model development environment. An improved set of 2-D analytical boundary conditions for submicron MOS technology is developed through using exact information from numerical simulations. In addition to the accurate modeling of 2-D potential boundary conditions, the model provides a framework for further enhancements in the context of technology evolution. Specifically, the methodology is general and can be extended to a variety of technologically complex submicron structures, for example, source/drain tip implants (LDD-type devices) and a variety of other blanket and locally implanted structures
Keywords :
electronic engineering computing; insulated gate field effect transistors; metal-insulator-semiconductor devices; semiconductor device models; 2D device analysis; LDD-type devices; blanket structures; boundary conditions; locally implanted structures; model development environment; numerical simulations; source/drain tip implants; submicron MOS technology; submicron device model; Analytical models; Boundary conditions; Circuit simulation; Circuit synthesis; Context modeling; Coupled mode analysis; Design automation; Implants; Information analysis; Memory; Numerical simulation; Physics; Semiconductor process modeling; Threshold voltage; Two dimensional displays;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
