DocumentCode :
1163342
Title :
Computation of steady-state CMOS latchup characteristics
Author :
Coughran, William M., Jr. ; Pinto, Mark R. ; Smith, R. Kent
Author_Institution :
AT&T Bell Labs., Murray Hill, NJ, USA
Volume :
7
Issue :
2
fYear :
1988
fDate :
2/1/1988 12:00:00 AM
Firstpage :
307
Lastpage :
323
Abstract :
Robust computational techniques are presented for steady-state characterization of CMOS latchup via numerical device simulation. Of specific interest are efficient means of accurately evaluating knees in I-V characteristics, corresponding to latchup triggering and holding points. Making use of predictor-corrector continuation procedures and special initial-guess strategies, more than an order of magnitude improvement in computational efficiency is achieved over previous approaches. It is shown that for some latchup problems, these methods are essential due to their unique ability to trace characteristics that are multivalued in both I and V . Simulated results for both triggering and holding characteristics of a VLSI CMOS process are presented, from which primary structural dependencies are identified and new physical insight is obtained
Keywords :
CMOS integrated circuits; VLSI; circuit analysis computing; predictor-corrector methods; CMOS latchup; I-V characteristics knees; VLSI CMOS process; computational efficiency; holding points; initial-guess strategies; latchup triggering; numerical device simulation; predictor-corrector continuation procedures; robust computation; steady-state characterization; structural dependencies; CMOS process; Charge carrier processes; Circuit simulation; Computational efficiency; Computational modeling; Electron mobility; Knee; Numerical simulation; Robustness; Steady-state; Very large scale integration; Voltage;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.3162
Filename :
3162
Link To Document :
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