Title :
High-performance vertical-power DMOSFETs with selectively silicided gate and source regions
Author :
Shenai, Krishna ; Piacente, Patricia A. ; Korman, Charles S. ; Baliga, Bayant J.
Author_Institution :
General Electric. Corp. Res. & Dev., Schenectady, NY, USA
fDate :
4/1/1989 12:00:00 AM
Abstract :
A power FET (field-effect transistor) structure with selectively silicided gate and source region is described. This structure simultaneously lowers the gate sheet-resistance and the source contact resistance. The gate-source isolation was provided by plasma etching conformally deposited chemical vapor deposition (CVD) oxide using a photoresist mask. This structure has resulted in an order of magnitude improvement in the gate sheet resistance and about 25% improvements in the device´s on-resistance (the resistance when conducting in the on-state) compared to previously reported nonsilicided conventional power FETs. Extremely low-resistance Al-TiW-TiSi/sub 2/ metallurgy with in situ sputter etching of the silicide surface prior to TiW deposition contributed to the reduction in the on-state resistance. Vertical-power DMOSFETs (double-diffused MOSFET) fabricated using this technology have a specific on-resistance of 0.53 Omega cm/sup 2/ for devices capable of blocking 50 V in the off state.<>
Keywords :
contact resistance; insulated gate field effect transistors; metallisation; power transistors; semiconductor technology; sputter etching; Al-TiW-TiSi/sub 2/ metallurgy; CVD oxide; double-diffused MOSFET; gate sheet-resistance; gate-source isolation; in situ sputter etching; on-resistance; photoresist mask; plasma etching; power FET; selectively silicided gate; selectivity silicided source; source contact resistance; vertical power DMOSFET; Chemical vapor deposition; Contact resistance; Etching; FETs; Plasma applications; Plasma chemistry; Plasma devices; Plasma sources; Resists; Surface resistance;
Journal_Title :
Electron Device Letters, IEEE
