Macromodeling CMOS circuits for timing simulation

A macromodeling and timing simulation technique is presented that allows fast and accurate delay calculations for CMOS circuits. This method is well suited for delay calculations of regular structure VLSI circuits, as well as circuits designed from standard cell libraries. Timing models for both logic gate and transmission gate circuit forms are developed. Typical delay times were within 5% for logic gate circuits and 10% for transmission gate circuits when compared with SPICE results. The execution time of experimental simulator was over two orders of magnitude faster than SPICE.<>