The Impact of Strain Technology on FUSI Gate SOI CMOSFET

Author

Yeh, Wen-Kuan ; Wang, Jean-An ; Tsai, Ming-Hsing ; Lin, Chien-Ting ; Chen, Po-Ying

Author_Institution

Dept. of Electr. Eng., Nat. Univ. of Kaohsiung, Kaohsiung

Volume

9

Issue

1

fYear

2009

fDate

3/1/2009 12:00:00 AM

Firstpage

74

Lastpage

79

Abstract

In this paper, the impact of strain engineering on device performance and reliability for fully silicide gate silicon-on-insulator CMOSFET was investigated. With characterizing device´s electrical property after hot carrier (HC) and positive/negative bias instability voltage stressing, we found similar enhancement on device performance but different behavior on voltage-stressing-induced device degradation for n/pMOSFETs. Related noise analysis and charge pumping techniques were used to investigate the strain-induced oxide defect which will accelerate device degradation after long-time HC voltage stressing and/or bias instability voltage stressing.

Keywords

CMOS integrated circuits; MOSFET; hot carriers; semiconductor device reliability; silicon-on-insulator; FUSI gate SOI CMOSFET reliability; charge pumping techniques; fully silicide gate silicon-on-insulator; hot carrier; negative bias instability voltage stressing; positive bias instability; strain-induced oxide defect; Fully silicide (FUSI); hot carrier (HC) and bias instability; strain engineering; tensile-strain and compressive-strain contact etch stop layer (CESL);

fLanguage

English

Journal_Title

Device and Materials Reliability, IEEE Transactions on

Publisher

ieee

ISSN

1530-4388

Type

jour

DOI

10.1109/TDMR.2008.2010622

Filename

4785210