Abstract :
A floating gate MOSFET has been designed to minimise the tunnelling current density injected through the oxide between two polysilicon layers by using local field enhancement provided from a bump structure. Compared to the floating gate device introduced by Thomsen, the modified floating gate which is fabricated in the same standard 2 μm double-polysilicon CMOS technology, reduces the programming voltage by 2.4 V and the erasing voltage by 1.4 V
