• DocumentCode
    1164457
  • Title

    Floating gate MOSFET with reduced programming voltage

  • Author

    Johnson, L.G.

  • Volume
    30
  • Issue
    18
  • fYear
    1994
  • fDate
    9/1/1994 12:00:00 AM
  • Firstpage
    1536
  • Lastpage
    1537
  • Abstract
    A floating gate MOSFET has been designed to minimise the tunnelling current density injected through the oxide between two polysilicon layers by using local field enhancement provided from a bump structure. Compared to the floating gate device introduced by Thomsen, the modified floating gate which is fabricated in the same standard 2 μm double-polysilicon CMOS technology, reduces the programming voltage by 2.4 V and the erasing voltage by 1.4 V
  • Keywords
    insulated gate field effect transistors; semiconductor storage; tunnelling; 2 micron; Si-SiO2; bump structure; double-polysilicon CMOS technology; erasing voltage; floating gate MOSFET; injected tunnelling current density; local field enhancement; oxide; programming voltage;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19941027
  • Filename
    317063
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1164457