Simplified parallel decision feedback equalisation for CCITT V.32/V.32 bis coded modems

A simplified parallel decision feedback equaliser (SPDFE) with the 32/64/128 AMPM CCITT trellis code is considered. The SPDFE detector consists of a whitened matched filter (WMF) and a reduced parallel decision feedback equaliser incorporated in the Viterbi decoder. The bit error rate simulation results show substantial improvement over the conventional detector with a linear equaliser and a separate Viterbi algorithm, although the implementation complexity remains the same.