High performance DMA controller for ultra HDTV video codecs

Innovative video solutions are required for many more customer centric new solutions (video conferencing, video surveillance, transcoding, streaming video etc). Increasing frame rate and frame size demands more DDR bandwidth. For example, Video processing engine (IVAHD) needs close to 3GByte/sec (encoder) of system bandwidth to support 4K@30fps. With concurrent multimedia sub-systems it is more important to have efficient data transfer between IVAHD shared Level2 Memory (SL2) and DDR. Amount of data, 2D nature of data, 2D data byte alignment conflicting with interconnect word (16Byte) alignment could not be addressed by the generic DMAs. This paper discusses about the DMA engine (VDMA) running at 266MHz which facilitates IVAHD in 4K processing per LCU (16×16) within 200 cycles. The final design in 28nm CMOS process is expected to consume 4mw of encode power and take around 0.50 mm2 after actual place & route (consisting of 1280 KG with 24 context each of size 128 Byte.