DocumentCode :
1165473
Title :
Performance analysis of single-buffered multistage interconnection networks
Author :
Hsiao, Shuo-Hsien ; Chen, C. Y Roger
Author_Institution :
IBM Corp., Austin, TX, USA
Volume :
42
Issue :
9
fYear :
1994
fDate :
9/1/1994 12:00:00 AM
Firstpage :
2722
Lastpage :
2729
Abstract :
A new model for the performance evaluation of single-buffered multistage interconnection networks (MINs) is proposed. Previous models proposed in solving this problem are either not accurate enough or only applicable to a special case where the switching elements (SEs) are 2×2 crossbars. This new model allows the analysis of a MIN with SEs of arbitrary sizes (i.e., a×a) and, through extensive simulations, has been shown to be very accurate. Since only three states are required at each stage of a MIN, this model is efficient computationally
Keywords :
packet switching; performance evaluation; switching networks; packet switching; performance analysis; performance evaluation model; simulations; single-buffered multistage interconnection networks; switching elements; Buffer storage; Communication switching; Computational modeling; Costs; Multiprocessing systems; Multiprocessor interconnection networks; Packet switching; Performance analysis; Petri nets; Switching circuits;
fLanguage :
English
Journal_Title :
Communications, IEEE Transactions on
Publisher :
ieee
ISSN :
0090-6778
Type :
jour
DOI :
10.1109/26.317413
Filename :
317413
Link To Document :
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