Variable bandwidth DPLL bit synchronizer with rapid acquisition implemented as a finite state machine

Author

Brügel, Helmuth ; Driessen, Peter F.

Author_Institution

Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada

Volume

42

Issue

9

fYear

1994

fDate

9/1/1994 12:00:00 AM

Firstpage

2751

Lastpage

2759

Abstract

A digital PLL bit synchronizer with variable loop bandwidth for rapid acquisition and good tracking performance is proposed, and its performance analyzed using Markov chain techniques. Results are presented for the distributions of acquisition time and time to first bit slip in terms of state transition probabilities. For burst mode data, results for the timing error and bit error rate as a function of the preamble bit number are obtained. All results are evaluated by repeated matrix products and verified by simulation. Comparison of the variable bandwidth DPLL to a fixed bandwidth DPLL shows significantly faster acquisition for a given tracking performance

Keywords

Markov processes; circuit switching; digital communication systems; finite state machines; multi-access systems; phase-locked loops; probability; signal processing; synchronisation; Markov chain techniques; acquisition time distribution; bit error; burst mode data; digital PLL bit synchronizer; finite state machine; fixed bandwidth DPLL; performance analysis; preamble bit number; rapid acquisition; repeated matrix products; simulation; state transition probabilities; time to first bit slip; timing error rate; tracking performance; variable loop bandwidth; Automata; Bandwidth; Detectors; Filters; Gain; Performance analysis; Phase detection; Phase locked loops; Timing; Tracking loops;

fLanguage

English

Journal_Title

Communications, IEEE Transactions on

Publisher

ieee

ISSN

0090-6778

Type

jour

DOI

10.1109/26.317416

Filename

317416