DocumentCode :
1165607
Title :
Automated Interface Refinement for Compositional Verification
Author :
Yao, Haiqiong ; Zheng, Hao
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL
Volume :
28
Issue :
3
fYear :
2009
fDate :
3/1/2009 12:00:00 AM
Firstpage :
433
Lastpage :
446
Abstract :
Compositional verification is essential for verifying large systems. However, approximate environments are needed when verifying the constituent modules in a system. Effective compositional verification requires finding a simple but accurate over approximate environment for each module. Otherwise, many verification failures may be produced, therefore incurring high computational penalty for distinguishing the false failures from the real ones. This paper presents an automated method to refine the state space of each module within an over approximate environment. This method is sound as long as an over approximate environment is found for each module at the beginning of the verification process, and it has less restrictions on system partitioning. It is also coupled with several state-space reduction techniques for better results. Experiments of this method on several large asynchronous designs show promising results.
Keywords :
asynchronous circuits; modules; program verification; asynchronous designs; automated interface refinement; compositional verification; state-space reduction; system partitioning; Abstraction refinement; circuit verification; compositional verification; formal method; logic verification; model checking;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2009.2012531
Filename :
4785335
Link To Document :
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