Double–Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits

In this paper, we describe a new transition fault model for synchronous sequential circuits. Similar to previous models, it addresses the fact that delayed signal-transitions span multiple clock cycles when a test sequence is applied at-speed. It addresses this issue in a different way than earlier models. The model requires the activation of single stuck-at faults with opposite stuck-at values on the same line g at consecutive time units. In addition, it requires the detection of both faults (as single faults) at the same or later time units. Due to the activation of the faults at consecutive time units, there is a 1 rarr 0 or 0 rarr 1 transition at the fault site g. Since both faults are eventually detected, a deviation from the expected value at either the first or second time unit due to a delay fault on g or due to transitions that started earlier and did not settle will be (or is likely to be) detected. The model can be used together with other models to increase the confidence that delay defects will be detected. As an added advantage, the model helps detect other types of faults that require two-pattern tests, such as transistor stuck-open faults.