• DocumentCode
    1165765
  • Title

    Iterative placement improvement by network flow methods

  • Author

    Doll, Konrad ; Johannes, Frank M. ; Antreich, Kurt J.

  • Author_Institution
    Dept. of Electr. Eng., Tech. Univ. Munchen, Germany
  • Volume
    13
  • Issue
    10
  • fYear
    1994
  • fDate
    10/1/1994 12:00:00 AM
  • Firstpage
    1189
  • Lastpage
    1200
  • Abstract
    We describe an efficient iterative improvement procedure for row-based cell placement with special emphasis on the objective function used to model net lengths. Two new net models are introduced and we prove theoretically that the net models are accurate approximations of the widely used half perimeter of a rectangle enclosing all pins of a net. In addition, unlike the half perimeter model, our net models allow us to compute costs for assigning cells to locations independently for all cells to be placed simultaneously. This offers our algorithm an important advantage compared to other iterative improvement techniques: many cells can be placed simultaneously by formulating placement as a network flow problem. This makes our algorithm more independent from a processing sequence than standard iterative improvement techniques. Finally, we compare our method to some existing algorithms including TimberWolfSC 5.4. We ran all of the algorithms on the SIGDA Benchmark Suite. We found that our method produced solutions with up to 23% less layout area while using an order of magnitude less running time compared to TimberWolfSC 5.4
  • Keywords
    application specific integrated circuits; circuit layout CAD; iterative methods; logic CAD; logic arrays; network routing; ASICs; SIGDA Benchmark Suite; half perimeter; iterative placement improvement; layout area; net lengths; net models; network flow methods; objective function; processing sequence; row-based cell placement; running time; Algorithm design and analysis; Application specific integrated circuits; Costs; Integrated circuit synthesis; Iterative algorithms; Iterative methods; Partitioning algorithms; Pins; Radio access networks; Routing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.317462
  • Filename
    317462