Time-domain macromodels for VLSI interconnect analysis

Author

Kim, Seok-Yoon ; Gopal, Nanda ; Pillage, Lawrence T.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

Volume

13

Issue

10

fYear

1994

fDate

10/1/1994 12:00:00 AM

Firstpage

1257

Lastpage

1270

Abstract

This paper presents a method of obtaining time-domain macromodels of VLSI interconnection networks for circuit simulation. The goal of this work is to include interconnect parasitics in a circuit simulation as efficiently as possible, without significantly compromising accuracy. Stability issues and enhancements to incorporate transmission line interconnects are also discussed. A unified circuit simulation framework, incorporating different classes of interconnects and based on the proposed macromodels, is described. The simplicity and generality of the macromodels is demonstrated through examples employing RC- and RLC-interconnects

Keywords

VLSI; circuit analysis computing; equivalent circuits; multiport networks; stability; time-domain analysis; transmission line theory; RC-interconnects; RLC-interconnects; VLSI interconnect analysis; circuit simulation; interconnect parasitics; stability; time-domain macromodels; transmission line interconnects; unified circuit simulation framework; Analytical models; Circuit simulation; Computational modeling; Function approximation; Integrated circuit interconnections; RLC circuits; Time domain analysis; Timing; USA Councils; Very large scale integration;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.317469

Filename

317469