2D cache architecture for motion compensation in a 4K Ultra-HD AVC and HEVC video codec system

Motion Compensation in AVC or HEVC Video codec requires reference pixels stored in the external SDRAM and interpolates it to form the Predictor Image. This is a significant chunk (70-80%) of the total SDRAM bandwidth and hence drives the bandwidth requirements. There is lot of overlap between the reference data required for every partition. This paper describes 2D or a block based caching scheme which exploits the commonality of reference pixel fetches across various partitions and thereby reducing the SDRAM bandwidth and power. Prior techniques heavily rely on using a video CPU to achieve this and still can do this only partially. This technique helps in reducing the LPDDR2 SDRAM power for a 4k Ultra-HD decoder by up to 70 mW and bandwidth by 800 MB/s (50% reduction) and increasing the typical 1080p30 HDMI playback time by 2 hours.