Strained-SOI n-Channel Transistor With Silicon–Carbon Source/Drain Regions for Carrier Transport Enhancement

A novel 80 nm gate length strained-Si n-channel transistor structure with lattice-mismatched source and drain (S/D) formed on thin-body silicon-on-insulator substrate is reported. The strained transistor features silicon-carbon (Si_1-yC_y) S/D regions, which are pseudomorphically grown by selective epitaxy. The incorporated carbon mole fraction y is 0.01. The lattice mismatch between Si_0.99C_0.01 and Si results in lateral tensile strain and vertical compressive strain in the Si channel region, both contributing to substantial electron mobility enhancement. The implementation of the Si_0.99C_0.01 stressors provides a substantial drive current I_Dsat enhancement of 11% over a control transistor at a gate length of 80 nm and a width of ~1.1 mum, while the enhancement for the linear drive current I_Dlin is approximately two times larger. Pulse measurements were also performed to correct for self-heating effects