An Ultralow-Power 10-Gbits/s LVDS Output Driver

This paper describes a new topology and implementation of a 10-Gbits/s low-voltage differential-signaling (LVDS) voltage-mode output driver designed for high-speed data-transfer applications. Using a positive-feedback technique, the driver achieves ultralow-power operation while maintaining the proper internal chip impedance required for matching the line impedance. As a result, signal reflection is minimized, and good signal integrity is achieved. The driver, which consists of a predriver and an output stage, consumes a total of 15.63-mW at-speed power. In measurements, the driver, which was a part of an equalizer chip, achieved a peak-to-peak jitter of 11 ps at 10 Gbits/s and a return-loss performance of less than -15 dB. It provides a single-ended output swing of 400 mV and a common-mode voltage of 1.25 V, which are compliant with LVDS standards. The chip is fabricated in a standard 2.5-V/1.2-V SiGe BiCMOS technology with 100-GHz peak ft and is packaged in a commercial LLP package.