• DocumentCode
    1167648
  • Title

    Hardware-Efficient Systolization of DA-Based Calculation of Finite Digital Convolution

  • Author

    Meher, Pramod Kumar

  • Author_Institution
    Sch. of Comput. Eng., Nanyang Technol. Univ.
  • Volume
    53
  • Issue
    8
  • fYear
    2006
  • Firstpage
    707
  • Lastpage
    711
  • Abstract
    Novel one- and two-dimensional systolic structures are designed for computation of circular convolution using distributed arithmetic (DA). The proposed structures involve significantly less memory and less area-delay complexity compared with the existing DA-based structures for circular convolution. Besides, it is shown that the proposed systolic designs for circular convolution can be used for computation of linear convolution as well
  • Keywords
    VLSI; convolution; distributed arithmetic; parallel algorithms; systolic arrays; DA; VLSI; circular convolution; distributed arithmetic; finite digital convolution calculation; hardware-efficient systolization; linear convolution; systolic array; systolic design; systolic structures; Convolution; Digital arithmetic; Digital signal processing; Digital signal processing chips; Distributed computing; Hardware; Pipeline processing; Read only memory; Systolic arrays; Very large scale integration; Circular convolution; VLSI; linear convolution; systolic array;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Express Briefs, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-7747
  • Type

    jour

  • DOI
    10.1109/TCSII.2006.877277
  • Filename
    1683985
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1167648