An All-MOS High-Linearity Voltage-to-Frequency Converter Chip With 520-kHz/V Sensitivity

Author

Wang, Chua-Chin ; Lee, Tzung-Je ; Li, Chi-Chen ; Hu, Ron

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung

Volume

53

Issue

8

fYear

2006

Firstpage

744

Lastpage

747

Abstract

An all-MOS linear voltage-to-frequency converter (VFC) chip with 520-kHz/V sensitivity is presented in this paper. This circuit converts an input voltage into frequency by charging and discharging a capacitor. An all-MOS voltage window comparator (VWC) with reduced propagation delay is designed to improve the linearity of traditional VFCs. The propagation delay of the VWC is discussed to resolve the tradeoff between bandwidth and linearity of VFC. The proposed VFC is verified on silicon using the Taiwan Semiconductor Manufacturing Company 1P5M 0.25-mum process. The measurement results show that the linearity error is less than 1%, and the sensitivity is 520 kHz/V at an input voltage range from 0.1 to 0.8 V

Keywords

MOS analogue integrated circuits; circuit optimisation; comparators (circuits); linearisation techniques; voltage-frequency convertors; 0.1 to 0.8 V; 0.25 micron; MOS; VFC; VWC; charging capacitor; discharging a capacitor; high-linearity voltage-to-frequency converter chip; reduced propagation delay; voltage window comparator; Bandwidth; Capacitors; Circuits; Frequency conversion; Linearity; Manufacturing processes; Propagation delay; Semiconductor device manufacture; Silicon; Voltage; Linearity; sensitivity; voltage window comparator (VWC); voltage-to-frequency converter (VFC);

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2006.876375

Filename

1683992