Arbitration and shuffling algorithm for processing multiple commands in SDRAM controller

In this paper, we propose an algorithm of arbitration and shuffling of requests for a memory controller which enables high bandwidth, low latency and low power consumption in systems with SoC network protocols that support outstanding address and out-of-order completion transactions. The memory access commands are stored in a queue, analyzed and shuffled in order to minimize activating new rows and to reduce the power consumption in the proposed architecture. It also adjusts the priority of processing commands if the network protocol supports QoS. We compare the performance of the proposed algorithm for the various memory access patterns.