Title :
Characterization of Upset-Induced Degradation of Error-Mitigated High-Speed I/O´s Using Fault Injection on SRAM Based FPGAs
Author :
Rezgui, Sana ; Swift, Gary M. ; Lesea, Austin
Author_Institution :
Xilinx Inc., San Jose, CA
Abstract :
Fault-injection experiments on Virtex-IItrade FPGAs quantify failure and degradation modes in I/O channels incorporating triple module redundancy (TMR). With increasing frequency (to 100 MHz), full TMR under both I/O standards investigated (LVCMOS at 3.3V and 1.8V) shows more configuration bits have a measurable detrimental performance effect when in error
Keywords :
SRAM chips; error analysis; field programmable gate arrays; integrated circuit testing; radiation hardening (electronics); redundancy; FPGA; I-O channel; SRAM; Virtex-II; detrimental performance; error-mitigation; fault injection; field programmable gate array; triple module redundancy; upset degradation; Circuit faults; Circuit simulation; Degradation; Field programmable gate arrays; Frequency measurement; Logic; Measurement standards; Random access memory; Redundancy; Voltage; Fault injection; field programmable gate arrays (FPGAs); upset mitigation; upset simulation;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2006.876510
